When power is applied to an integrated circuit device, a power-on reset circuit typically holds the device in a known state, sometimes maintaining elements of the device in a high impedance state, until voltage has risen to a level at which elements of the device are known to operate properly. The reset circuit then typically releases the device from its reset state so that it can begin operation. Integrated circuit devices also typically include means for a user or some part of the device to provide a reset signal during operation, so that the device may be reset without removing power. Typically, a user reset can be invoked by asserting a specific signal on a user pin. For example, this pin may be normally held in a logical high state but when brought to a logical low level (active low reset), the signal on the pin causes the device to be reset.
FIG. 1 shows a prior art circuit for controlling a user programmable logic device in which configuration data are loaded and registers are preset in response to a reset signal. The circuit of FIG. 1 uses an OR gate 14 with one inverted input to combine an output signal from Vdd detect circuit 11 with a user-generated master reset signal MRX on line 13 to generate a global reset signal on line 15. FIG. 1A shows a circuit associated with FIG. 1. AND gate 101 receives the MRX signal on line 13 and also receives the RESET signal on line 15. In addition to these two signals, in one embodiment AND gate 101 also receives two additional signals CONLD and PRELD. The CONLD signal indicates that configuration data are being loaded into the chip and the PRELD signal indicates that registers in the chip are being preset. FIG. 4 shows a timing diagram associated with the circuit of FIGS. 1 and 1A. As shown in FIG. 4, the READY signal responds to the low-going MRX signal by also going low. AND gate 101 provides a low output signal, which places the chip into a not-ready state in which no processing occurs and outputs are in a high impedance state. When the MRX signal again goes high after time t1, RESET goes low such that AND gate 101 can respond to other signals. The high-going edge of the MRX signal causes the CONLD signal to go high, which initiates loading of configuration data. After time t2, when loading of configuration data is complete, the CONLD signal goes low, which causes the PRELD signal to go high, in turn initiating preloading of the registers during time t3. But a high CONLD signal and a high PRELD signal cause AND gate 101 to maintain the chip in a not ready state (the READY signal remains low) until configuration data have been reloaded into the chip and internal registers have been preloaded. Only when the PRELD signal again goes low can the READY signal again go high, placing the chip into operating condition.
In some applications, the timing sequence of FIG. 4 produces an undesirable delay t4 before the chip can be put into operation. Therefore it is desirable to reduce the time t4 the READY signal is held low.